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Magazine Name : Ieee Transactions On Very Large Scale Intergration (Vlsi) Systems
Year : 1998Volume number : 06Issue:02
The Transmogrifier-2 A 1 Million Gare Rapid-Prototyping Systm.(Article) Subject:
Architecture
Author:
D. R
Galloway
D. M
Lewis
page:
188
-
198
Ant-On Yards: Fpga/Mpu Hybrid Architecture For Telecommunications Data Processing.(Article) Subject:
Codesign
,
Field Programmable Gate Arrary (Fpga)
Author:
T
Miyazaki
A
Tsutsui
page:
199
-
211
Low Overhead Fault - Tolerant Fpga Systems.(Article) Subject:
Field Progammable Gate Arary (Fpga)
Author:
W. H M
Smith
J
Lach
page:
212
-
221
Fpga Routing And Routability Estimation Via Boolean Satisfibility.(Article) Subject:
Computer -Aided Design
Author:
R. A
Rutenbar
R. G
Wood
page:
222
-
231
Some Experiments Abour Wave Pipelining On Fpga'S.(Article) Subject:
Arithmetic Unit
Author:
S. L
Buedo
E. I
Boemo
page:
232
-
237
Signal Processingat 250 Mhz Using Hih-Performance Fpga'S.(Article) Subject:
Correlators
,
Event Horizon
Author:
B. Von
Herzen
page:
238
-
246
Improving Functional Density Usingrun-Time Circuit Reconfiguration.(Article) Subject:
Adaptive Computing
Author:
M. J
Virthlin
B. L
Hutchings
page:
247
-
256
Fault-Tolereant Self-Oragnization Map Implemented By Wafer-Scale Integration.(Article) Subject:
Defect
,
Neural Network
Author:
I
Hachiya
M
Yasunaga
page:
257
-
265
Power Estimation Of Embedded Systems: A Hardware/Software Codesign Approach.(Article) Subject:
Embadded System
Author:
P
Gubian
W
Fornaciari
page:
266
-
275
Testing Confiurable Lut-Based Fpga'S.(Article) Subject:
C-Testability
Author:
P
Gubian
W
Fornaciari
page:
276
-
283
A Mimd-Based Video Signal Proesing Architecutre Suitable For Large Area Integration And A 16.6-Cm2 Monolithic Implementation.(Article) Subject:
Author:
K
Herrmann
J
Ottestedt
page:
284
-
291
A Vlsi Inner Product Macroacell.(Article) Subject:
Author:
L
Dadda
L
Breveglieri
page:
292
-
298
Energy Optimiztion Of Multilevel Cache Architecutes For Risc And Cisc Processors.(Article) Subject:
Author:
P. T
Balsara
U
Ko
page:
299
-
308
Zero-Aliasing Space Compaction Of Test Responses Using Multiple Parity Signatues.(Article) Subject:
Eleastoplastic Modeling
Author:
J. P
Hayes
K
Chakrabarty
page:
309
-
313
Time Multiplexed Coror Image Processing Based On A Cnn With Cell-State Outputs.(Article) Subject:
Author:
J. P. D
Gyvez
page:
314
-
322
A Rated -Clock Test Method For Path Delay Faults.(Article) Subject:
Author:
P
Agrawal
S
Bose
page:
323
-
331
Concurrent Falult Simulatin On Message Passing Multicomputers.(Article) Subject:
Author:
S
Bose
P
Agrawal
page:
332
-
342